1. Field of the Invention
This invention generally relates to systems and methods for inspection of a specimen such as a semiconductor wafer. Certain embodiments relate to methods for correlating backside and frontside defects detected on a specimen and classification of backside defects.
2. Description of the Related Art
Fabricating semiconductor devices such as logic and memory devices includes processing a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process which typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes may include chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
During each semiconductor fabrication process, defects such as particulate contamination and pattern defects may be introduced into the semiconductor devices. Defects may be isolated in a single semiconductor device on a semiconductor wafer containing several hundred semiconductor devices. More commonly, the defects occur in many semiconductor devices formed across an entire semiconductor wafer. Different types of defects may result from different process or tool marginalities. For example, defects that are caused by un-optimized processes or tools, incompatibility of materials, up-optimized materials, and/or un-optimized characteristics of materials are commonly referred to as “systematic defects.” Defects that occur unexpectedly or unpredictably over time, which may be caused by tool failure, variations in processing materials or chemicals, particles, contamination, and other environmental marginalities are often referred to as “random defects.”
Successful fabrication of semiconductor devices is often limited by the presence of defects in the semiconductor devices. Monitoring semiconductor fabrication processes over time has become increasingly important in the industry to improve or maintain yield as the dimensions of semiconductor devices shrink. Macro-level defect inspection may be used to detect yield-limiting large scale defects on a wafer. Such defects may be commonly referred to as “macro defects” and are typically characterized as having a lateral dimension of greater than about 25 μm. Such large scale defects may include resist or developer problems such as lifting resist, thin resist, extra resist coverage, incomplete or missing resist, which may be caused by clogged dispense nozzles or an incorrect process sequence, and developer or water spots. Additional examples of defects may include regions of defocus that may be caused by particles on the backside of a wafer, reticle errors such as tilted reticles, out-of-focus exposure or incorrectly selected reticles, scratches, pattern integrity problems such as over or under developing of the resist, contamination such as particles or fibers, and non-uniform or incomplete edge bead removal (“EBR”). Other defects are commonly referred to as “hot spots,” which generally refers to a resist exposure defect which may be caused, for example, by a depth of focus limitation of an exposure tool, an exposure tool malfunction, a non-planar surface of the semiconductor wafer at the time of exposure, foreign material on a backside of the semiconductor wafer or on a surface of a supporting device, or a design constraint.
Macro-level defect inspection may involve inspecting all of the product wafers in a lot or only a number of product wafers in each lot because such defects may be particularly deleterious to the yield of semiconductor manufacturing processes. In addition, the high cost associated with semiconductor device fabrication necessitates macro-level defect inspection such that the effects of yield-limiting large scale defects may be minimized. Macro-level defect inspection of product wafers typically includes only inspection on the frontside of the product wafers (i.e., the surface of the wafers on which the semiconductor devices are being formed). The surface of the product wafers on which semiconductor devices are not formed is commonly referred to as the “backside” of the wafers. Macro-level defect inspection is typically performed on the backside of non-product semiconductor wafers (i.e., un-patterned wafers or “monitor wafers”), which have been run through a process tool, to monitor the conditions of the process tool.
Micro-level defect inspection may be used to detect any defects having dimensions smaller than the dimensions of macro-level defects. Such inspection is typically performed with different tools than systems designed for macro-level defect inspection because of the different resolution requirements needed to detect the different sized defects. Micro-level defect inspection is typically used to inspect the frontside of semiconductor wafers. Micro-level defect inspection may also be used to detect defects on the frontside of patterned and unpatterned wafers. For example, micro-level defect inspection may be used to analyze a resist coating process or a resist develop process on a unpatterned wafer. Alternatively, micro-level defect inspection may be used to analyze an exposure tool and exposure process on a patterned wafer. Wafers for these two micro-level defect inspection may be performed with non-product wafers. In this manner, these non-product wafers may be reworked and reused multiple times, and abnormal process and/or tool deviations may be readily detected and corrected prior to manufacturing devices on product wafers. Micro-level defect inspection (in addition to, or as an alternative to macro-level defect inspection) may also be performed periodically on the frontside of product wafers to monitor drift in the process and/or the tool and to monitor the presence of random defects on the frontside of the product wafers.